Peak detector circuits have a variety of applications, including in cellular telephones. In general, a peak detector operates by detecting a time varying input voltage and storing charge on a capacitor to produce a voltage equal to the maximum detected input voltage. Another known type of peak detector converts input voltage to a current and integrates the current. This second type of peak detector may be implemented in complementary metal oxide semiconductor (CMOS) technology, which enhances its applicability. For example, the CMOS peak detector may be integrated on a single integrated circuit with other circuit elements to reduce the cost and size of the overall circuit. Also, the CMOS peak detector may be operated at relatively low operating voltages, such as 3.0 V.
However, known CMOS peak detector designs have been limited to relatively low speed or low frequency applications. In one known design, the maximum input frequency is only 12 MHz, which is too low for many applications.
Accordingly, there is a need in the art for an improved peak detector circuit operable at input frequencies above 12 MHz.